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CS35L00
2.7 W Mono Class-D Audio Amplifier with Low Idle Current
CS35L00 Features
Hybrid Class-D Architecture
General Description
The CS35L00 is a 2.7 W high efficiency Hybrid Class-D audio amplifier with low idle current consumption and a selectable gain. The CS35L00 features an advanced closed-loop architecture to provide 0.02% THD+N at 1 W and -75 dB PSRR at 217 Hz. A flexible Hybrid Class-D output stage offers four modes of operation: Standard Class-D (SD) mode offers full audio bandwidth and high audio performance; Hybrid Class-D (HD) mode offers a substantial reduction in idle power consumption with an integrated ClassH controller; Reduced Frequency Class-D (FSD) mode reduces the output switching frequency, producing lower electromagnetic interference (EMI); and Reduced Frequency Hybrid Class-D (FHD) mode produces both the lower idle power consumption of HD mode and the reduced EMI benefits of FSD mode. Requiring minimal external components and PCB space, the CS35L00 is available in a 3.0 mm x 3.0 mm, 10-pin DFN package in Commercial grade (-10C to +70C). Please see "Ordering Information" on page 33 for package options and gain configurations.

- <1 mA Quiescent Current - 1 x 2.7 W into 4 (10% THD+N) - 1 x 2.1 W into 4 (1% THD+N) - 1 x 1.6 W into 8 (10% THD+N) - 1 x 1.3 W into 8 (1% THD+N) Advanced Closed-loop Modulation - 98 dB Signal-to-Noise Ratio (A-Weighted) - 0.02% THD+N @ 1 W (SD & HD Mode) Integrated Protection and Automatic Recovery for Output Short-circuit and Thermal Overload Thermally Enhanced 10-pin DFN Package with Pin-selectable Gain of +6 dB or +12 dB Pop and Click Suppression
Common Applications
Laptops Netbooks Portable Navigation Devices Active Speakers Portable Gaming
MODE
LDO Filter
Low Drop-Out Voltage Regulator
VBATT 2.5V - 5V
Class-H Controller Shutdown Gate Drivers Audio In + Gain Select Audio In Gain Gain Advanced Modulator Gate Drivers
Speaker Out + Speaker Out -
Internal Oscillator
Short Circuit/Thermal Protection
GND
Advance Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved)
MAY '10 DS906A2
CS35L00
TABLE OF CONTENTS
1. PIN DESCRIPTIONS FOR CS35L00 ..................................................................................................... 5 2. DIGITAL PIN CONFIGURATIONS ......................................................................................................... 6 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 7 4. CHARACTERISTICS & SPECIFICATIONS ........................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8 ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES ................................................... 9 ELECTRICAL CHARACTERISTICS - SD MODE ................................................................................ 10 ELECTRICAL CHARACTERISTICS - FSD MODE .............................................................................. 11 ELECTRICAL CHARACTERISTICS - HD MODE ................................................................................ 12 ELECTRICAL CHARACTERISTICS - FHD MODE ............................................................................. 13 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 14 POWER-UP & POWER-DOWN CHARACTERISTICS ........................................................................ 14 5. APPLICATIONS ................................................................................................................................... 15 5.1 MODE Descriptions ....................................................................................................................... 15 5.1.1 Standard Class D Modes of Operation .................................................................................. 15 5.1.1.1 SD Mode .................................................................................................................... 15 5.1.1.2 FSD Mode .................................................................................................................. 15 5.1.2 Hybrid Class D Modes of Operation ...................................................................................... 15 5.1.2.1 HD Mode .................................................................................................................... 16 5.1.2.2 FHD Mode ................................................................................................................. 16 5.2 Reducing the Gain with External Series Resistors ........................................................................ 16 5.3 Output Filtering with the CS35L00 ................................................................................................. 17 5.3.1 Reduced Filter Order with the CS35L00 ............................................................................... 17 5.3.2 Filter Component Selection ................................................................................................... 17 5.3.3 Output Filter Power Dissipation Considerations .................................................................... 18 5.3.3.1 Conduction Losses for All Modes of Operation ......................................................... 18 5.3.3.2 Switching Losses in SD/FSD Mode ........................................................................... 18 5.3.3.3 Switching Losses in HD/FHD. .................................................................................... 18 5.4 Power-Up and Power-Down .......................................................................................................... 19 5.4.1 Recommended Power-Up Sequence .................................................................................... 19 5.4.1.1 Zero Crossing on Power-Up Functionality ................................................................. 19 5.4.2 Recommended Power-Down Sequence ............................................................................... 20 5.5 Over Temperature Protection ........................................................................................................ 20 6. TYPICAL PERFORMANCE PLOTS ..................................................................................................... 21 6.1 SD Mode Typical Performance Plots ............................................................................................. 21 6.2 FSD Mode Typical Performance Plots ........................................................................................... 23 6.3 HD Mode Typical Performance Plots ............................................................................................. 25 6.4 FHD Mode Typical Performance Plots ........................................................................................... 27 7. PARAMETER DEFINITIONS ................................................................................................................ 29 8. PACKAGING AND THERMAL INFORMATION .................................................................................. 30 8.1 Package Drawings and Dimensions .............................................................................................. 30 8.2 Recommend PCB Footprint and Routing Configuration ................................................................ 31 8.3 Package Thermal Performance ..................................................................................................... 31 8.4 DFN Thermal Pad .......................................................................................................................... 31 8.4.1 Determining Maximum Ambient Temperature ....................................................................... 32 9. ORDERING INFORMATION ................................................................................................................ 33 10. REVISION HISTORY .......................................................................................................................... 33
2
DS906A2
CS35L00
LIST OF FIGURES
Figure 1.Top View of DFN Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Typical Connection Diagram for SD & FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.Typical Connection Diagram for HD & FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4.Adjusting Gain via External Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5.Optional Output Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6.Power-Up Timing with Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7.Power Up Timing without Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8.THD+N vs. Output Power - SD Mode RL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9.THD+N vs. Output Power - SD Mode RL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10.THD+N vs. Frequency - SD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11.THD+N vs. Frequency - SD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12.THD+N vs. Frequency - SD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13.Frequency Response - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14.Idle Current Draw vs. VBATT - SD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15.Output Power vs. VBATT - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16.Efficiency vs. Output Power - SD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 17.Efficiency vs. Output Power - SD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18.Supply Current vs. Output Power - SD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 19.Supply Current vs. Output Power - SD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 20.THD+N vs. Output Power - FSD Mode RL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 21.THD+N vs. Output Power - FSD Mode RL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 22.THD+N vs. Frequency - FSD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 23.THD+N vs. Frequency - FSD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 24.THD+N vs. Frequency - FSD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 25.Frequency Response - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 26.Idle Current Draw vs. VBATT - FSD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 27.Output Power vs. VBATT - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 28.Efficiency vs. Output Power - FSD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 29.Efficiency vs. Output Power - FSD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 30.Supply Current vs. Output Power - FSD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 31.Supply Current vs. Output Power - FSD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 32.THD+N vs. Output Power - HD Mode RL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 33.THD+N vs. Output Power - HD Mode RL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 34.THD+N vs. Frequency - HD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 35.THD+N vs. Frequency - HD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 36.THD+N vs. Frequency - HD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 37.Frequency Response- HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 38.Idle Current Draw vs. VBATT - HD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 39.Output Power vs. VBATT - HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 40.Efficiency vs. Output Power - HD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 41.Efficiency vs. Output Power - HD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 42.Supply Current vs. Output Power - HD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 43.Supply Current vs. Output Power - HD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 44.THD+N vs. Output Power - FHD Mode RL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 45.THD+N vs. Output Power - FHD Mode RL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 46.THD+N vs. Frequency - FHD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 47.THD+N vs. Frequency - FHD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 48.THD+N vs. Frequency - FHD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 49.Frequency Response - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 50.Idle Current Draw vs. VBATT - FHD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 51.Output Power vs. VBATT - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 52.Efficiency vs. Output Power - FHD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DS906A2 3
CS35L00
Figure 53.Efficiency vs. Output Power - FHD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 54.Supply Current vs. Output Power - FHD Mode RL = 8 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 55.Supply Current vs. Output Power - FHD Mode RL = 4 + 33 H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIST OF TABLES
Table 1. LFILT+ and MODE Operation Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. JA Specification for Typical PCB Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4
DS906A2
CS35L00 1. PIN DESCRIPTIONS FOR CS35L00
SD
1
10
OUT+
IN-
2
9
GND
LFILT+
3
Thermal Pad
8
VBATT
IN+
4
7
GAIN_SEL
MODE
5
6
OUT-
Figure 1. Top View of DFN Pin Out (Looking down through package)
Pin Name
SD INLFILT+ IN+ MODE OUTGAIN_SEL VBATT GND OUT+ Thermal Pad
#
1 2 3 4 5 6 7 8 9 10 -
Pin Description
Shutdown (Input) - Pulling this pin low places the CS35L00 in shutdown. Negative Analog Input (Input) - Differential negative audio signal input Low Drop Out Regulator Filter (Output) - Bypass capacitor connection point for internal LDO. Connecting this net to VBATT places the device into SD mode. Positive Analog Input (Input) - Differential positive audio signal input. Switching Mode (Input) - Controls the output switching modes of the CS35L00. Negative PWM Output (Output) - Differential negative PWM output. Gain Select (Input) - Sets the gain of the amplifier. When pulled low, gain is +12 dB. When pulled high, gain is +6 dB. Positive Analog Power Supply (Input) - Positive power supply input. Ground (Input) - Power supply ground. Positive PWM Output (Output) - Differential Positive PWM output. Thermal Pad (Input) - Thermal relief pad for optimized heat dissipation. Connect to GND. See "DFN Thermal Pad" on page 31 for more information.
DS906A2
5
CS35L00 2. DIGITAL PIN CONFIGURATIONS
See (Note 1) and (Note 2) below the table. Power Supply
VBATT
I/O Name
SD MODE GAIN_SEL
Pin #
1 5 7
Direction
Input Input Input
Internal Connections
No Internal Pull Up No Internal Pull Up No Internal Pull Up
Configuration
Hysteresis on CMOS Input Hysteresis on CMOS Input Hysteresis on CMOS Input
Note: 1. Refer to specification table "Digital Interface Specifications & Characteristics" on page 14 for details on the digital I/O characteristics. 2. I/O voltage levels must not exceed the voltage listed in table "Absolute Maximum Ratings" on page 8.
6
DS906A2
CS35L00 3. TYPICAL CONNECTION DIAGRAMS
2.5V - 5V
0.1uF 10uF
LFILT+
VBATT
System Controller
MODE SD OUT+
Audio In+
AIN+ AIN+
OUT-
Audio In-
GAIN_SEL
Connect to VBATT for +6dB Gain or GND for +12dB Gain
GND
Figure 2. Typical Connection Diagram for SD & FSD Mode
2.5V - 5V
(Note 3)
1uF
10uF
0.1uF
LFILT+
VBATT
System Controller
MODE SD OUT+
Audio In+
AIN+ AIN+
OUT-
Audio In-
GAIN_SEL
Connect to VBATT for +6dB Gain or GND for +12dB Gain
GND
Figure 3. Typical Connection Diagram for HD & FHD Mode Note: 3. The value of the capacitance connected to the LFILT+ net should not exceed 4.7 F. Presence of a capacitance above 4.7 F will prevent proper HD and FHD operation.
DS906A2
7
CS35L00 4. CHARACTERISTICS & SPECIFICATIONS
Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; Input Signal = 997 Hz Differential Sine; TA = 25C; VBATT = 5 V; RL = 8 ; 10 Hz to 20 kHz Measurement Bandwidth; Measurements taken with AES17 measurement filter and Audio Precision AUX-0025 passive filter.
RECOMMENDED OPERATING CONDITIONS
GND = 0 V; All voltages with respect to ground. Please see (Note 4).
Parameters DC Power Supply
Supply Voltage
Symbol
VBATT TA TJ
Min
2.5 -10 -10
Typ
5.0 -
Max
5.5 +70 +150
Units
V C C
Temperature
Ambient Temperature Junction Temperature
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; All voltages with respect to ground. Parameters DC Power Supply
Supply Voltage LFILT+ Current (Note 5) VBATT IVDREG Iin TA Tstg -0.3 6.0 10 10 +125 +150 V
Symbol
Min
Max
Units
A
mA C C
Inputs
Input Current -20 -65
Temperature
Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 4. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. 5. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device.
8
DS906A2
CS35L00 ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES
Parameters
Max. Current from LFILT+ LFILT+ Output Impedance VBATT Limit for HD/FHD Mode (Note 7) (Note 6)
Symbol
ILFILT+ ZLFILT+ VBLIM VIN-LDO
Test Conditions
Min
-
Typ
10 0.7 3.0 0.014*VBATT 0.027*VBATT 0.09 0.18 800 1.0 +/-2 12 6 0.05 380 150 100 1.9 10
Max Units
A VDC Vrms Vrms Vrms Vrms ms V mV dB dB A m C ms V s
Input Level for Entering LDO Operation in HD/FHD Modes (Note 8)
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
-
Input Level for Entering VBATT Operation GAIN_SEL = Low (12 dB) V in HD/FHD Modes (Note 9) IN-VBATT GAIN_SEL = High (6 dB) LDO Entry Time Delay LDO Level for HD/FHD Modes Output Offset Voltage Amplifier Gain Shutdown Supply Current MOSFET On Resistance Thermal Error Threshold Thermal Error Retry Time (Note 10) (Note 10) tLDO VLDO VOFFSET Inputs AC coupled to GND AV IA(SD) GAIN_SEL = Low GAIN_SEL = High SD = Low
RDS(ON) Ibias = 0.5 A TTE RTE UVLO GD Output Levels at 10% THD+N 4 + 33H 8 + 33H Load Load VBATT = 5 VDC VBATT = 3.7 VDC VBATT = 5 VDC VBATT = 3.7 VDC
Under Voltage Lockout Threshold Total Group Delay
-
89 88 81 80
-
% % % %
Operating Efficiency
Note: 6. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device. 7. When VBATT is below this threshold (VBLIM), operation is automatically restricted to SD mode. 8. When operating in HD or FHD mode and the differential input voltage remains below the input level threshold (VIN-LDO) for a period of time (tLDO), the PWM outputs will be powered by the internally generated LDO supply (VLDO). 9. When operating in HD or FHD mode and the differential input voltage is above this input level threshold (VIN-VBATT), the PWM outputs will powered directly from the VBATT supply. 10. Refer to Section 5.5 for more information on Thermal Error functionality.
DS906A2
9
CS35L00 ELECTRICAL CHARACTERISTICS - SD MODE
Parameters Symbol Test Conditions
THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC)
Min
(Note 12) -
Typ
1.32/0.92/0.70 2.17/1.50/1.14 1.65/1.15/0.89 2.72/1.89/1.45 0.02 75 75 55
Max Units
W W W W % dB dB dB
Output Power (Continuous Average)
PO
Total Harmonic Distortion + Noise Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio A-Weighted
THD+N PO = 1.0 W PSRR CMRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz Vripple = 1 VPP, fripple = 217 Hz Inputs AC Coupled to Ground, Referenced to 1% THD+N GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINICNA GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AIN-
SNRA
94 95
-
dB dB
Idle Channel Noise A-Weighted
-
54 49
-
Vrms Vrms
Idle Channel Noise Frequency Response Output Switching Frequency
ICN FR fsw1
GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 20 Hz to 20 kHz
-0.1 -
100 100 0 192
0.4 -
Vrms Vrms dB kHz
AIN+ connected AIN-, No Output Load Idle Current Draw (Note 11) IIDLE VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 1.06 1.00 0.97 65 100 0.84/0.70/0.62 1.68/1.40/1.22 mA mA mA k k Vrms Vrms
Input Impedance, Single Ended
ZIN
Input Voltage @ 1 % THD+N
VICLIP
10
DS906A2
CS35L00 ELECTRICAL CHARACTERISTICS - FSD MODE
Parameters Symbol Test Conditions
THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC)
Min
(Note 12) -
Typ
1.27/0.88/0.68 2.09/1.45/1.10 1.63/1.14/0.88 2.69/1.87/1.43 0.13 75 75 55
Max Units
W W W W % dB dB dB
Output Power (Continuous Average)
PO
Total Harmonic Distortion + Noise THD+N PO = 1.0 W Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio A-Weighted PSRR CMRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz Vripple = 1 VPP, fripple = 217 Hz Inputs AC Coupled to Ground, Referenced to 1% THD+N GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINICNA GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINIdle Channel Noise Frequency Response Output Switching Frequency ICN FR fsw2 AIN+ connected AIN-, No Output Load Idle Current Draw (Note 11) IIDLE VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 20 Hz to 20 kHz
SNRA
80 80
-
dB dB
Idle Channel Noise A-Weighted
-
300 300
-
Vrms Vrms
-4.0 -
660 660 0 76
0.5 -
Vrms Vrms dB kHz
-
0.88 0.86 0.85 160 240 0.82/0.69/0.60 1.64/1.37/1.20
-
mA mA mA k k Vrms Vrms
Input Impedance, Single Ended
ZIN
Input Voltage @ 1 % THD+N
VICLIP
Note: 11. Idle Current Draw (IIDLE) is specified without any output filtering. Refer to Section 5.3 on page 17 for information on output filtering.
DS906A2
11
CS35L00 ELECTRICAL CHARACTERISTICS - HD MODE
Parameters Symbol Test Conditions
THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC)
Min
(Note 12) -
Typ
1.32/0.92/0.70 2.17/1.50/1.15 1.65/1.15/0.89 2.72/1.89/1.45 0.02 75 75 55
Max Units
W W W W % dB dB dB
Output Power (Continuous Average)
PO
Total Harmonic Distortion + Noise THD+N PO = 1.0 W Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio A-Weighted PSRR CMRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz Vripple = 1 VPP, fripple = 217 Hz Inputs AC Coupled to Ground, Referenced to 1% THD+N GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINICNA GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINIdle Channel Noise Frequency Response Output Switching Frequency ICN FR fsw1 AIN+ connected AIN-, No Output Load Idle Current Draw (Note 13) IIDLE VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 20 Hz to 20 kHz
SNRA
97 98
-
dB dB
Idle Channel Noise A-Weighted
-
49 43
-
Vrms Vrms
-0.1 -
86 85 0 192
0.4 -
Vrms Vrms dB kHz
-
0.94 0.94 0.94 65 100 0.84/0.70/0.62 1.68/1.40/1.22
-
mA mA mA k k Vrms Vrms
Input Impedance, Single Ended
ZIN
Input Voltage @ 1 % THD+N
VICLIP
12
DS906A2
CS35L00 ELECTRICAL CHARACTERISTICS - FHD MODE
Parameters Symbol Test Conditions
THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC)
Min
(Note 12) -
Typ
1.27/0.88/0.68 2.09/1.45/1.10 1.63/1.14/0.88 2.69/1.87/1.43 0.15 75 75 55
Max Units
W W W W % dB dB dB
Output Power (Continuous Average)
PO
Total Harmonic Distortion + Noise THD+N PO = 1.0 W Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio A-Weighted PSRR CMRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz Vripple = 1 VPP, fripple = 217 Hz Inputs AC Coupled to Ground, Referenced to 1% THD+N GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINICNA GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) AIN+ connected to AINIdle Channel Noise Frequency Response Output Switching Frequency Output Switching Frequency ICN FR fsw1 fsw2 GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 20 Hz to 20 kHz Input level below VIN-LDO Input level above VIN-VBATT AIN+ connected AIN-, No Output Load Idle Current Draw (Note 13) IIDLE VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB)
SNRA
92 93
-
dB dB
Idle Channel Noise A-Weighted
-
71 66
-
Vrms Vrms
-4.0 -
125 125 0 192 76
0.5 -
Vrms Vrms dB kHz kHz
-
0.94 0.94 0.94 160 240 0.82/0.69/0.60 1.64/1.37/1.20
-
mA mA mA k k Vrms Vrms
Input Impedance, Single Ended
ZIN
Input Voltage @ 1 % THD+N
VICLIP
Note: 12. SNRA dB is referenced to the output signal amplitude resulting in the specified output power at THD+N <1%. See "Parameter Definitions" on page 29 for more information. 13. Idle Current Draw (IIDLE) is specified without any output filtering. Refer to Section 5.3 on page 17 for information on output filtering. At idle, the output devices will switch at the same rate in HD and FHD mode. FHD only changes the output switching frequency when the input levels are above the "Input Level for Entering VBATT Operation in HD/FHD Modes (VIN-VBATT) given in "Electrical Characteristics - All Operational Modes" on page 9.
DS906A2
13
CS35L00 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters
Input Leakage Current Input Capacitance SD Pulse Width Requirement Logic I/Os (Applicable to GAIN_SEL, MODE, and SD) High-Level Input Voltage Low-Level Input Voltage VIH VIL 0.7*VBATT 0.3*VBATT V V
Symbol
Iin
Min
1
Max
10 10 -
Units
A pF ms
POWER-UP & POWER-DOWN CHARACTERISTICS
Parameters
Start-Up Time (Note 14)
Symbol
tstart ttimeout toff
Test Conditions
After "Low" to "High" SD Pin transition edge No audio input applied After "High" to "Low" SD Pin transition edge
Min
-
Typ
18 25 1
Max Units
ms ms ms
Zero Crossing Power-Up Timeout Power-Down Time
Note: 14. Start-Up Time (tstart) refers to the internal start-up time from when SD is released to when the device is ready to activate the PWM outputs. The total power-up time from SD release to the PWM outputs becoming active will vary based on the input signal, not exceeding the Start-Up Time + Zero Crossing Power-Up Timeout (tstart + ttimeout). For more information refer to Section 5.4.
14
DS906A2
CS35L00 5. APPLICATIONS
5.1 MODE Descriptions
The CS35L00 device can be operated in one of four operating modes, determined by the MODE pin and the LFILT+ pin. The four modes of operation are Standard Class-D operation (SD), Reduced Frequency Standard Class-D operation (FSD), Hybrid Class-D operation (HD), and Reduced Frequency Hybrid ClassD operation (FHD). Each of these modes can be leveraged to optimize different performance criteria in an array of applications.
MODE connected to:
GND LFILT+ connected to: VBATT Reduced Frequency Class-D Mode (FSD) VBATT Standard Class-D Mode (SD)
Filter Cap to Ground
Reduced Frequency Hybrid Class-D Mode (FHD)
Hybrid Class-D Mode (HD)
Table 1. LFILT+ and MODE Operation Configurations
5.1.1
Standard Class D Modes of Operation 5.1.1.1 SD Mode
Standard Class-D (SD) mode supports full audio bandwidth with very good SNR and THD+N performance. This mode of operation is characterized by a traditional closed loop, analog modulated ClassD amplifier. With an output switching frequency of 192 kHz, this mode ensures flat frequency response across the entire audio frequency range.
5.1.1.2
FSD Mode
The Reduced Frequency Class-D (FSD) mode provides competitive audio performance and a reduction in radiated emissions by decreasing the switching frequency of the output devices to 76 kHz. This reduction in switching frequency reduces the high frequency energy being created by the output switching events. Idle channel noise is slightly higher in this mode of operation than SD mode, with the trade-off being better EMI performance and power consumption.
5.1.2
Hybrid Class D Modes of Operation
Hybrid Class-D and Reduced Frequency Hybrid Class-D modes of operation allows the rail voltage for the output devices to switch between a high voltage net and a low voltage net depending on the audio content being amplified. This is explained in more detail in Section 5.1.2.1 and Section 5.1.2.2. Operation in these modes requires that the voltage present on the VBATT pin be above the level listed as "VBATT Limit for HD/FHD Mode (VBLIM)" in "Electrical Characteristics - All Operational Modes" on page 9. If it is not, HD and FHD modes of operation of the device will automatically be disabled and operation will be limited to the SD mode of operation.
DS906A2
15
CS35L00
In both HD and FHD mode, the value of the capacitance connected to the LFILT+ pin must not exceed 4.7 F. If this value is greater than 4.7 F, it will prevent the rail voltage of the output devices from transitioning properly between VBATT and the internal LDO.
5.1.2.1
HD Mode
Hybrid Class-D mode (HD) provides competitive analog performance with a substantial reduction in idle power dissipation and radiation emissions. In this mode, the output switches at 192 kHz and a secondary supply is derived from VBATT using an internal 1.0 VDC low drop-out linear regulator (LDO). When the output signal is at a low amplitude, the Class-D output stage begins to switch from the lower rail voltage created by the internal LDO. This not only decreases idle power consumption when output capacitors are used, but also reduces electromagnetic emissions by reducing the amplitude of the square waves being created at the output of the CS35L00 when operating at low amplitude or idle power.
5.1.2.2
FHD Mode
The Reduced Frequency Hybrid Class-D (FHD) mode provides the best overall EMI performance and the lowest power consumption with slightly decreased frequency response near the top frequency range of the audio band, for high amplitude signals. In this mode of operation, the output switching frequency is reduced to 76 kHz during high amplitude transients on the output. The threshold at which this transition from 192 kHz to 76 kHz switching rate occurs is given as the Input Level Threshold for FHD Operation in "Electrical Characteristics - FHD Mode" on page 13. Combined with the lower amplitude switching offered by the Hybrid design, this reduction in switching energy dramatically reduces the emissions levels of the output stage and its associated components.
5.2
Reducing the Gain with External Series Resistors
If necessary, it is possible to decrease the gain of the CS35L00 by adding series resistors to the audio input signal as is shown in Figure 4 below.
Audio In+
RIN
x
AIN+ AIN-
Audio In-
RIN
x
Figure 4. Adjusting Gain via External Series Resistance If input resistors are added, the new gain of the amplifier can be determined by the following equation:
Z IN A V adjusted = A V - 20 log -------------------------- Z IN + Z EXT
Where: AV(adjusted) = The new, adjusted gain of the system
16
DS906A2
CS35L00
ZIN = Input impedance of the device being used (See "Electrical Characteristics - SD Mode" on page 10, "Electrical Characteristics - FSD Mode" on page 11, "Electrical Characteristics - HD Mode" on page 12, or "Electrical Characteristics - FHD Mode" on page 13 for this value.) ZEXT = Value of the resistor added in series with the inputs AV = Original gain of the device being used (See "Electrical Characteristics - All Operational Modes" on page 9 for this value.)
5.3
Output Filtering with the CS35L00
The CS35L00 is specifically designed to minimize radiated electromagnetic interference (EMI) signals. All of the devices are capable of meeting all stated data sheet performance numbers with no special filtering required. Additionally, the device has shown to be below the compliance limits of both FCC and CISPR testing with no external filtering required. Ultimately, compliance with any radiated emissions requirements depends significantly on the entire system under test. In applications were system-level trade-offs, such as compromised component layout or lengthy speaker wires, have increased emissions levels, a passive output filter can be added to the outputs of the device in order to decrease EMI levels.
5.3.1
Reduced Filter Order with the CS35L00
In applications which require an output filter, the unique design of the CS35L00 allows a much smaller, less expensive output filter to be used than what is normally found in Class D amplifiers. In contrast to a second order filter implemented with a series inductive element (traditional inductor or ferrite beads) and a shunt capacitive element, basic filtering for the CS35L00 is accomplished by a single-order capacitive element attached to the OUTx terminals. This is highlighted in Figure 5 below. Of course, if the system requires more aggressive filtering, a ferrite bead can be added in series with the outputs to further attenuate system level noise.
OUT+
x
LFILT
OUT+
C FILT
x
C FILT
OUT-
x
OUTLFILT C FILT
x
C FILT
Traditional 2nd Order Optional Filtering
CS35L00's Minimized Optional Filtering
Figure 5. Optional Output Filter Components
5.3.2
Filter Component Selection
Usually, the need for output filtering is determined after the system under test has failed EMI testing. During this testing, problem frequencies are easily identified by the peaks which appear in the spectral plots gathered in the EMI testing. Selection of the filter components should ensure that shunt elements (i.e. CFILT in Figure 5 on page 17) present a very low impedance at the frequency corresponding to the tallest peak in the spectral plot. If needed, series components such as ferrite beads (i.e. LFILT in Figure 5 on page 17) should be chosen to present a very high impedance at the frequency corresponding to the tallest peak in the spectral plot. Careful attention should be paid to the current carrying capabilities of any included ferrite beads and the impedance of the ferrite beads in the audio band. A proper trade-off in ferrite bead selection is one that
DS906A2
17
CS35L00
allows the ferrite bead to sufficiently attenuate the problematic high-frequency emissions without compromising audio performance.
5.3.3
Output Filter Power Dissipation Considerations
In systems without inductive series elements like inductors or ferrite beads, power losses in the output filter are equal to the switching losses that occur in the system due to the cyclical charging and discharging of capacitors connected to the amplifier outputs. In systems that require an inductive series element, conducted losses also occur due to the series impedance added to the output path.
5.3.3.1
Conduction Losses for All Modes of Operation
For all modes of operation (SD, FSD, HD, and FHD), conduction losses are governed by the following equation:
P = I2Z
Where: P = Power dissipated in the series impedance. I = RMS AC output current Z = impedance of the series element at the frequency of the AC current This equation neglects any series impedances presented by the PCB traces or speaker wires in the output path.
5.3.3.2
Switching Losses in SD/FSD Mode 1 P = -- CV 2 f 2
Switching losses in SD/FSD Mode are governed by the equation
Where: P = Power dissipated in the capacitor (neglecting parasites). C = Value of filtering capacitor V = Peak voltage developed across the capacitor f = Switching frequency of the outputs These calculations are straightforward, as the peak voltage is simply the voltage level attached to VBATT, the capacitor is the value of capacitor that has been added for filtering (neglecting parasitic board capacitances), and the frequency is 192 kHz for SD and 76 kHz for FSD, respectively.
5.3.3.3
Switching Losses in HD/FHD.
Many factors affect the switching losses when the device is operated in HD/FHD mode. These factors include the frequency of the content being amplified, the voltage level of VBATT, and the amplitude of the output signal will factor into both the voltage presented across the capacitors and the frequency at which the capacitors are charged or discharged.
18
DS906A2
CS35L00
Static signals (i.e. sine waves at a fixed amplitude) are easier to consider than are dynamic signals (i.e. musical content), as they are governed by the same equation as that listed in Section 5.3.3.1 and Section 5.3.3.2 on page 18. Modifications to that equation are limited to the voltage term (V) and the frequency term (f), depending on whether the static input signal amplitude is causing the output devices to switch at 76 kHz or 192 kHz, and to operate off of the VBATT supply or off of the internally generated LDO. It is important to note that the HD and FHD modes offer significant improvement over traditional Class D in idle power dissipation when an external output filter is necessary. This is because the voltage term (V) is significantly reduced in HD and FHD mode. As can be seen in the equation, this is notable because reduction in the operating voltage reduces power losses not linearly, but instead exponentially- due to the voltage squared term (V2). It is also notable that when operated at high output levels, FHD modes also offers unique improvement in output filter losses, due to reducing the switching frequency (f) at higher output levels.
5.4
Power-Up and Power-Down
When pulled to a logic low state, the SD pin tristates the outputs and shuts down the CS35L00 device, putting it into a low power mode.
5.4.1
Recommended Power-Up Sequence
1. With the SD pin pulled low, apply power to the CS35L00 and wait for the power supply to be stable. 2. Set the SD pin high to begin normal operation.
5.4.1.1
Zero Crossing on Power-Up Functionality
The CS35L00 implements an input-signal zero-crossing detection function that is enabled during powerup. This function is designed to prevent audible artifacts and eliminate any need to mute the amplifier's input audio signal during the power-up process. After a minimum start-up time of tstart, the CS35L00 will begin to detect input-signal zero-crossings. The amplifier will then enable its switching outputs at the time of the first detected input-signal zero-crossing transition. If no input-signal zero-crossing is detected before ttimeout, the zero-crossing function will timeout and the outputs will begin switching immediately. Both tstart and ttimeout are specified in "Power-Up & Power-Down Characteristics" on page 14.
IN+/VIH VIL
IN+/VIH VIL
SD
SD
tstart ttimeout
tstart
ttimeout
VBATT or VLDO
VBATT or VLDO
OUT+/Shut-Down / Low Power Mode Internal Start-Up Device Ready: Waiting for Zero Crossing Input Signal or ttimeout PWM OUT+/Active
OUT+/Shut-Down / Low Power Mode Internal Start-Up Device Ready: Waiting for Zero Crossing Input Signal or ttimeout PWM OUT+/Active
Figure 6. Power-Up Timing with Input Zero-Crossing
Figure 7. Power Up Timing without Input Zero-Crossing
DS906A2
19
CS35L00
5.4.2 Recommended Power-Down Sequence
1. Mute the audio supplied to the CS35L00. 2. Pull the SD pin low in order to reset the device and put it into the low power mode. 3. The power supply to the CS35L00 can now be removed.
5.5
Over Temperature Protection
The CS35L00 is internally protected against thermal overload. Built in die temperature sensing circuitry monitors the die temperature and will place the device into shut-down if thermal overload occurs. A thermal overload is characterized by the die temperature reaching the Thermal Error Threshold (TTE) at which time the outputs will tristate and shut down. If the device has entered into shut-down due to a thermal overload, the die temperature must remain below the Thermal Error Threshold (TTE) for the time specified by the Thermal Error Retry Time (RTE) in order for the device to automatically return to normal operation. Both TTE and RTE are specified in "Electrical Characteristics - All Operational Modes" on page 9.
20
DS906A2
CS35L00 6. TYPICAL PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; AV = 6 dB; Input Signal = 997 Hz Differential Sine; TA = 25C; VBATT = 5.0 V; RL = 8 ; 10 Hz to 20 kHz Measurement Bandwidth; Measurements taken with AES17 measurement filter and Audio Precision AUX-0025 passive filter.
6.1
10 5
SD Mode Typical Performance Plots
10 5
2
1
5.0 V 4.2 V 3.7 V
2
1
5.0 V 4.2 V 3.7 V
0.5
0.5
% 0.2
% 0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01 0.007 1m 2m 5m 10m 20m 50m W 100m 200m 500m 1 2
0.01 0.007 1m
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
3
Figure 8. THD+N vs. Output Power - SD Mode RL = 8
10 5
Figure 9. THD+N vs. Output Power - SD Mode RL = 4
10 5
2
2
1
1
0.5
0.5
0.75 W
0.2
0.2
%
0.1
1.0 W 0.1 W
%
0.1
0.05
0.05
0.1 W
0.02 0.01
0.02
0.01
0.005
0.005
0.5 W
0.002 0.001 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
0.5 W
0.002 0.001 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 10. THD+N vs. Frequency - SD Mode VBATT = 5.0 V
10 5
Figure 11. THD+N vs. Frequency - SD Mode VBATT = 4.2 V
+4 +3.5 +3
2
+2.5 +2 +1.5 +1
1
0.5
4
0.2 d B r A
+0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 20
%
0.1
0.625 W 0.1 W
0.05
0.02
8
0.01
0.005
0.002
0.5 W
50 100 200 500 Hz 1k 2k 5k 10k 20k
0.001 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 12. THD+N vs. Frequency - SD Mode VBATT = 3.7 V
Figure 13. Frequency Response - SD Mode
DS906A2
21
CS35L00
7.00 3.5
2200 pF
6.00 3.0
RL = 4 10% THD+N Ratio
5.00
2.5
Supply Current (mA)
Output Power (W)
4.00
2.0
1000 pF
3.00
RL = 4 1% THD+N Ratio
1.5
2.00
1.0
470 pF
1.00 0.5
RL = 8 10% THD+N Ratio RL = 8 1% THD+N Ratio
2.5 3.0 3.5 4.0 VBATT Supply Voltage (V) 4.5 5.0 5.5
No Filter
0.00 2.5 3 3.5 4 VBATT (V) 4.5 5 5.5 0.0
Figure 14. Idle Current Draw vs. VBATT - SD Mode RL = 8 + 33 H (Note 15)
100%
Figure 15. Output Power vs. VBATT - SD Mode
100%
90%
90%
80%
80%
3.7 V
70% 60% Efficiency (%)
4.2 V
5.0 V
70%
3.7 V
60% Efficiency (%) 50% 50%
4.2 V
5.0 V
40%
40%
30%
30%
20%
20%
10%
10%
0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0% 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 16. Efficiency vs. Output Power - SD Mode RL = 8 + 33 H
0.40
Figure 17. Efficiency vs. Output Power - SD Mode RL = 4 + 33 H
0.80
0.35
0.70
4.2 V
0.30
0.60
4.2 V 3.7 V
Current Consumption (A) 0.50
3.7 V
0.25 Supply Current (A)
5.0 V
0.20
5.0 V
0.40
0.15
0.30
0.10
0.20
0.05
0.10
0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0.00 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 18. Supply Current vs. Output Power - SD Mode RL = 8 + 33 H
Figure 19. Supply Current vs. Output Power - SD Mode RL = 4 + 33 H
Note: 15. "Idle Current Draw vs. VBATT - SD Mode" capacitor values refer to CFILT when configured as the "CS35L00's Minimized Optional Output Filter", shown in Figure 5 on page 17. 22 DS906A2
CS35L00
6.2
10 5
FSD Mode Typical Performance Plots
10 5
2
5.0 V 4.2 V 3.7 V
2
5.0 V 4.2 V 3.7 V
1
1
0.5 % 0.2 %
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01 1m
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
0.01 1m
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
3
Figure 20. THD+N vs. Output Power - FSD Mode RL = 8
10
Figure 21. THD+N vs. Output Power - FSD Mode RL = 4
10
5
5
2
2
1.0 W
1 1
0.75 W
0.5 % 0.2 %
0.5
0.1 W
0.2
0.1 W
0.1
0.1
0.05
0.05
0.02
0.5 W
50 100 200 500 Hz 1k 2k 5k 10k 20k
0.5 W
0.02
0.01 20
0.01 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 22. THD+N vs. Frequency - FSD Mode VBATT = 5.0 V
10
Figure 23. THD+N vs. Frequency - FSD Mode VBATT = 4.2 V
+4 +3.5
5 +3 +2.5 2
0.625 W
+2 +1.5 +1
4
1
0.5 % 0.2 d B r A
+0.5 +0 -0.5 -1
0.1 W
8
0.1 -1.5 -2 -2.5
0.05
0.02
0.5 W
50 100 200 500 Hz 1k 2k 5k 10k 20k
-3 -3.5
0.01 20
-4 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 24. THD+N vs. Frequency - FSD Mode VBATT = 3.7 V
Figure 25. Frequency Response - FSD Mode
DS906A2
23
CS35L00
3.50 3.5
3.00
2200 pF
3.0
2.50
2.5
RL = 4 10% THD+N Ratio
Supply Current (mA)
2.00
Output Power (W)
2.0
1000 pF
1.50
RL = 4 1% THD+N Ratio
1.5
1.00
1.0
470 pF
0.50 0.5
RL = 8 10% THD+N Ratio RL = 8 1% THD+N Ratio
2.5 3.0 3.5 4.0 VBATT Supply Voltage (V) 4.5 5.0 5.5
No Filter
0.00 2.5 3 3.5 4 VBATT (V) 4.5 5 5.5 0.0
Figure 26. Idle Current Draw vs. VBATT - FSD Mode RL = 8 + 33 H (Note 16)
100%
Figure 27. Output Power vs. VBATT - FSD Mode
100%
90%
90%
80%
80%
3.7 V
70% 60% Efficiency (%)
4.2 V
5.0 V
Efficiency (%)
70%
3.7 V
60% 50% 50%
4.2 V
5.0 V
40%
40%
30%
30%
20%
20%
10%
10%
0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0% 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 28. Efficiency vs. Output Power - FSD Mode RL = 8 + 33 H
0.40
Figure 29. Efficiency vs. Output Power - FSD Mode RL = 4 + 33 H
0.80
0.35
0.70
4.2 V
0.30
0.60
4.2 V 3.7 V
Current Consumption (A) 0.50
3.7 V
0.25 Supply Current (A)
5.0 V
0.20
5.0 V
0.40
0.15
0.30
0.10
0.20
0.05
0.10
0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0.00 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 30. Supply Current vs. Output Power - FSD Mode RL = 8 + 33 H
Figure 31. Supply Current vs. Output Power - FSD Mode RL = 4 + 33 H
Note: 16. "Idle Current Draw vs. VBATT - FSD Mode" capacitor values refer to CFILT when configured as the "CS35L00's Minimized Optional Output Filter", shown in Figure 5 on page 17. 24 DS906A2
CS35L00
6.3
10 5
HD Mode Typical Performance Plots
10 5
2
5.0 V 4.2 V 3.7 V
2
1
1
5.0 V 4.2 V 3.7 V
0.5
0.5
% 0.2
% 0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01 0.007 1m
0.01 0.007 1m
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
3
Figure 32. THD+N vs. Output Power - HD Mode RL = 8
10
T
Figure 33. THD+N vs. Output Power - HD Mode RL = 4
10
5
5
2
2
1
1
0.5
0.5
0.2
1.0 W
%
0.2
%
0.1
0.1
0.75 W 0.1 W
0.05
0.05
0.1 W
0.02 0.01
0.02
0.01
0.005
0.005
0.5 W
0.002 0.002 0.001 20 0.001 20 50 100 200 500 Hz
0.5 W
5k 10k 20k 1k 2k 5k 10k 20k
50
100
200
500 Hz
1k
2k
Figure 34. THD+N vs. Frequency - HD Mode VBATT = 5.0 V
10
Figure 35. THD+N vs. Frequency - HD Mode VBATT = 4.2 V
+4 +3.5 +3
5
2
+2.5 +2 +1.5 +1
1
0.5
4
0.2 d B r
+0.5 +0 -0.5 -1 -1.5 -2 -2.5
%
0.1
0.625 W
0.05
A
0.1 W
0.02 0.01
8
0.005
0.5 W
0.002 0.001 20
-3 -3.5 -4 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 36. THD+N vs. Frequency - HD Mode VBATT = 3.7 V
Figure 37. Frequency Response- HD Mode
DS906A2
25
CS35L00
4.00
3.5
3.50
3.0
3.00
RL = 4 10% THD+N Ratio
2.5
2.50
2200 pF
Output Power (W)
Supply Current (mA)
2.00
1000 pF
2.0
RL = 4 1% THD+N Ratio
1.5
1.50
1.00
1.0
0.50
470 pF No Filter
RL = 8 10% THD+N Ratio RL = 8 1% THD+N Ratio
2.5 3.0 3.5 4.0 VBATT Supply Voltage (V) 4.5 5.0 5.5
0.5
0.00 2.5 3 3.5 4 VBATT (V) 4.5 5 5.5
0.0
Figure 38. Idle Current Draw vs. VBATT - HD Mode RL = 8 + 33 H (Note 17)
100%
Figure 39. Output Power vs. VBATT - HD Mode
100%
90%
90%
80%
80%
3.7 V
70% 60% Efficiency (%)
4.2 V
5.0 V
70%
3.7 V
60% Efficiency (%) 50% 50%
4.2 V
5.0 V
40%
40%
30%
30%
20%
20%
10%
10%
0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0% 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 40. Efficiency vs. Output Power - HD Mode RL = 8 + 33 H
0.40
Figure 41. Efficiency vs. Output Power - HD Mode RL = 4 + 33 H
0.80
0.35
0.70
4.2 V
0.30
0.60
4.2 V 3.7 V
Current Consumption (A) 0.50
3.7 V
0.25 Supply Current (A)
5.0 V
0.20
5.0 V
0.40
0.15
0.30
0.10
0.20
0.05
0.10
0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0.00 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 42. Supply Current vs. Output Power - HD Mode RL = 8 + 33 H
Figure 43. Supply Current vs. Output Power - HD Mode RL = 4 + 33 H
Note: 17. "Idle Current Draw vs. VBATT - HD Mode" capacitor values refer to CFILT when configured as the "CS35L00's Minimized Optional Output Filter", shown in Figure 5 on page 17. When VBATT is below "VBATT Limit for HD/FHD Mode" (VBLIM), operation is restricted to SD Mode. 26 DS906A2
CS35L00
6.4
10 5
FHD Mode Typical Performance Plots
10 5
2
5.0 V 4.2 V 3.7 V
2
5.0 V 4.2 V 3.7 V
1
1
0.5 % 0.2 %
0.5
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01 1m
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
0.01 1m
2m
5m
10m
20m
50m W
100m
200m
500m
1
2
3
Figure 44. THD+N vs. Output Power - FHD Mode RL = 8
10
Figure 45. THD+N vs. Output Power - FHD Mode RL = 4
10
5
5
1.0 W
2 2 1
0.75 W
1
0.5 % 0.2
0.5 %
0.1 W
0.2
0.1 W
0.1
0.1
0.05
0.05
0.5 W
0.02 0.02 0.01 20 0.01 20
0.5 W
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 46. THD+N vs. Frequency - FHD Mode VBATT = 5.0 V
10
Figure 47. THD+N vs. Frequency - FHD Mode VBATT = 4.2 V
+4 +3.5
5
+3 +2.5
2
0.625 W
+2 +1.5
1
4
+1 +0.5 +0 -0.5 -1 -1.5 -2
0.5 % 0.2
d B r A
0.1 W
8
0.1
0.05 -2.5
0.02
0.5 W
50 100 200 500 Hz 1k 2k 5k 10k 20k
-3 -3.5 -4 20
0.01 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 48. THD+N vs. Frequency - FHD Mode VBATT = 3.7 V
Figure 49. Frequency Response - FHD Mode
DS906A2
27
CS35L00
4.00
3.5
3.50
3.0
3.00
2.5
RL = 4 10% THD+N Ratio
Supply Current (mA)
2.50
Output Power (W)
2200 pF 1000 pF
2.0
2.00
1.5
RL = 4 1% THD+N Ratio
1.50
1.00
1.0
470 pF
0.50
RL = 8 10% THD+N Ratio
0.5
No Filter
0.00 2.5 3 3.5 4 VBATT (V) 4.5 5 5.5
0.0 2.5 3.0
RL = 8 1% THD+N Ratio
3.5 4.0 VBATT Supply Voltage (V) 4.5 5.0 5.5
Figure 50. Idle Current Draw vs. VBATT - FHD Mode RL = 8 + 33 H (Note 18)
100%
Figure 51. Output Power vs. VBATT - FHD Mode
100%
90%
90%
80%
80%
3.7 V
4.2 V
5.0 V
70%
70%
3.7 V
60% Efficiency (%)
4.2 V
5.0 V
60% Efficiency (%)
50%
50%
40%
40%
30%
30%
20%
20%
10%
10%
0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0% 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 52. Efficiency vs. Output Power - FHD Mode RL = 8 + 33 H
0.40
Figure 53. Efficiency vs. Output Power - FHD Mode RL = 4 + 33 H
0.80
0.35
0.70
4.2 V
0.30
0.60
4.2 V 3.7 V
Current Consumption (A) 0.50
3.7 V
0.25 Supply Current (A)
5.0 V
0.20
5.0 V
0.40
0.15
0.30
0.10
0.20
0.05
0.10
0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W)
0.00 0 0.5 1 1.5 Output Power (W) 2 2.5 3
Figure 54. Supply Current vs. Output Power - FHD Mode RL = 8 + 33 H
Figure 55. Supply Current vs. Output Power - FHD Mode RL = 4 + 33 H
Note: 18. "Idle Current Draw vs. VBATT - FHD Mode" capacitor values refer to CFILT when configured as the "CS35L00's Minimized Optional Output Filtering" shown in Figure 5 on page 17. When VBATT is below "VBATT Limit for HD/FHD Mode" (VBLIM), operation is restricted to SD Mode. 28 DS906A2
CS35L00 7. PARAMETER DEFINITIONS
Signal to Noise Ratio (SNR) The ratio of the RMS value of the output signal, where Pout is equivalent to the specified output power at THD+N<1%, to the RMS value of the noise floor with no input signal applied and measured over the specified bandwidth, typically 20 Hz to 20 kHz. This measurement technique has been accepted by the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Idle Channel Noise (ICN) Measure of the signal present on the outputs of the device when no audio signal is presented to the input pins. For this test, both input pins are shorted together, setting the differential signal to them to zero.
DS906A2
29
CS35L00 8. PACKAGING AND THERMAL INFORMATION
8.1 Package Drawings and Dimensions (Note 19)
10 PIN DFN
DIM
A A1 D E L b e
MIN
0.034 0.000 0.114 0.114 0.014 0.008 --
INCHES NOM
0.035 0.001 0.118 0.118 0.016 0.009 0.019
MAX
0.037 0.002 0.122 0.122 0.018 0.012 --
MIN
0.850 0.000 2.900 2.900 0.350 0.200 --
MILLIMETERS NOM
0.900 0.020 3.000 3.000 0.400 0.250 0.500
NOTE MAX
0.950 0.050 3.100 3.100 0.450 0.300 -19 19 19 19 19 19
JEDEC #: MO-220 Controlling Dimension is Millimeters. Note: 19. Dimensioning and tolerance per ASME Y 14.5M-1994.
30
DS906A2
CS35L00
8.2 Recommend PCB Footprint and Routing Configuration
To ensure high-yield manufacturability, the PCB footprint for the CS35L00 should be constructed with strict adherence to the specifications given in IPC-610. Departure from this specification significantly increases the probability of solder bridging and other manufacturing defects. Routing of the traces into and out of the CS35L00 device should also be given consideration to avoid manufacturing issues.
8.3
Package Thermal Performance
Class D amplifiers, though highly efficient, produce heat through the process of amplifying the audio signal. As is well understood, the amount of heat is very small compared to that of traditional Class AB amplifiers. Even so, as power levels increase and package sizes decrease, careful consideration must be given to ensure that thermal energy is removed from the device as efficiently as possible so that its operating temperature is kept under its Over-Temperature Error Threshold. The thermal impedance, JA is a measurement of the impedance to the flow of thermal energy out of the device to the environment surrounding the device. This specification is directly related to the ability of the PCB to which the CS35L00 is attached to transfer the heat from the device. The thermal impedance from the junction of the device to the ambient surrounding the device and the thermal impedance from the device into the PCB is shown in Table 2. . Parameter (Note 20), (Note 21)
Junction to Ambient Thermal Impedance Junction to Printed Circuit Board Thermal Impedance
Symbol A PCB
Min
-
Typical
100 70
Max
-
Units
C/Watt C/Watt
Table 2. JA Specification for Typical PCB Designs Note: 20. Test Printed Circuit Board Assembly (PCBA) constructed in accordance with JEDEC standard JESD51-9. Two-signal, two-plane (2s2p) PCB used. 21. Test conducted with still air in accordance with JEDEC standards JESD51, JESD51-2A, and JESD518.
8.4
DFN Thermal Pad
The CS35L00 is available in a compact DFN package. The underside of the DFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to PGND. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers; the copper in these ground planes will act as a heat sink for the CS35L00.
DS906A2
31
CS35L00
8.4.1 Determining Maximum Ambient Temperature
To determine (to a first order approximation) the maximum ambient temperature in which the CS35L00 will operate, the following equations can be used:
T op = JA 1 - P max T max = T TE - T op
Where: Tmax = The maximum ambient temperature in which the device can operate. Top = The operating temperature of the device, given a dissipated power "Pmax" and a known thermal impedance "JA". TTE = The Over-Temperature Error Threshold, given in the "Characteristics & Specifications" section on page 8. JA = The thermal impedance of the device and PCB. (This value is highly subjective to a number of application specific scenarios. The numbers given in Table 2 on page 31 can be used for a first order approximation, but proper characterization of the application's specific PCB and supporting mechanicals is needed to increase the accuracy of the result achieved here.) Pmax = The maximum power at which the amplifier will be operated continuously. (For conservative estimates, the 10% THD+N rated power given in "Characteristics & Specifications" section on page 8 can be used. However, this method will predict higher operating temperatures than what may be seen in the application, since power content of audio signals is much smaller than that of the sine wave used to establish the power specifications.) = The efficiency of the device at the power Pmax. (A safe, conservative assumption is 85%)
32
DS906A2
CS35L00 9. ORDERING INFORMATION
Product Description Package Pb-Free Yes Grade Temp Range Container Order# CS35L00-CNZ CS35L00 2.9 W Mono Audio 10-DFN Amplifier with selectable gain Commercial -10 to +70C Rail
Tape and Reel CS35L00-CNZR
10.REVISION HISTORY
Release
A1 A2
Changes
Initial Release - Updated all output switching frequency references to fsw1 from 200 kHz to 192 kHz. - Updated all output switching frequency references to fsw2 from 80 kHz to 76 kHz. - Updated front page title, features, and common applications. - Updated front page block diagram. - Updated Section 3. Typical Connection Diagrams to show 10 F and 0.1 F power-supply decoupling capacitors. - Reorganized location of individual specifications in electrical characteristics tables based on measured device performance in different operational modes ("Electrical Characteristics - All Operational Modes" on page 9, "Electrical Characteristics - SD Mode" on page 10, "Electrical Characteristics - FSD Mode" on page 11, "Electrical Characteristics - HD Mode" on page 12, and "Electrical Characteristics - FHD Mode" on page 13). - The following specification changes have been made in "Electrical Characteristics - SD Mode" on page 10, "Electrical Characteristics - FSD Mode" on page 11, "Electrical Characteristics - HD Mode" on page 12, and "Electrical Characteristics - FHD Mode" on page 13: - Added "Common-Mode Rejection Ratio" test conditions (Vripple = 1 VPP and fripple = 217 Hz) - Updated "Signal to Noise Ratio" to be specified as A-Weighted - Updated "Idle Channel Noise" to be specified as both A-Weighted & Unweighted - Updated "Idle Current Draw" to be specified with no load at 3 voltages (5.0 V, 4.2 V, and 3.7 V) - Changed "Max Input Before Clipping specification to "Input Voltage @ 1 % THD+N" - Updated specification typical values for 1% Output Power, 10% Output Power, THD+N @ 1 W, SNR A-Weighted, Idle Channel Noise A-Weighted, Idle Channel Noise (unweighted), Frequency Response, Output Switching Frequency, Input Impedance, and Input Voltage @ 1% THD+N - Updated "Operating Efficiency" to be specified with 8 + 33 H and 4 + 33 H in "Electrical Characteristics - All Operational Modes" on page 9. - Modified "Power-Up Time" specification into "Start-Up Time" and "Zero Crossing Power-Up" and added a cross-reference in "Power-Up & Power-Down Characteristics" on page 14. - Moved power-up and power-down timing specifications from "Electrical Characteristics - All Operational Modes" on page 9 to their own specification table, "Power-Up & Power-Down Characteristics" on page 14. - Renamed "Thermal Error Wait Time (WTE)" to "Thermal Error Retry Time (RTE)" in "Electrical Characteristics - All Operational Modes" on page 9 and in Section 5.5 Over Temperature Protection and added (Note 10) Thermal Error cross reference from spec table to description section. - Updated "Operating Efficiency" specification () in "Electrical Characteristics - All Operational Modes" on page 9. - Updated "MOSFET On Resistance" specification (RDS(ON)) in "Electrical Characteristics - All Operational Modes" on page 9.
DS906A2
33
CS35L00
A2 - - - - - - - Updated Shutdown Supply Current specification (IA(SD)) in "Electrical Characteristics - All Operational Modes" on page 9. Added "MOSFET On Resistance" test conditions (Ibias = 0.5 A) in "Electrical Characteristics - All Operational Modes" on page 9. Section 5.1.1.1 SD Mode updated to remove references to edge rate control. Section 5.1.2.1 HD Mode updated to include fsw1 switching frequency and clarify the conditions under which radiated emissions gains occur. Added Section 6. Typical Performance Plots. Added Section 5.4 Power-Up and Power-Down. Modified "Input Level Threshold for HD/FHD Modes" to be split up into "Input Level for Entering LDO Operation in HD/FHD Modes" and "Input Level for Entering VBATT Operation in HD/FHD Modes" in "Electrical Characteristics - All Operational Modes" on page 9. Added "LDO Entry Time Delay" specification in "Electrical Characteristics - All Operational Modes" on page 9. Updated (Note 8) and added (Note 9) referring to the "Input Level Thresholds". Updated Section 5.5 Over Temperature Protection functional description. Updated out of date specification names, symbols, and cross-references in multiple locations throughout the document.
- - - -
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
34
DS906A2

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